Hello,
I have a Spartan-6 XC6SLX9 FPGA on testing board from ebay, FPGA is communicating with W5100 on WIZ812MJ board via direct bus interface mode. FPGA has 50MHz Xtal and divider is generating 25MHz clock for W5100. I have small hardware upgrade: original 25MHz Xtal is replaced by external clock from divider by 2 from 50MHz Xtal because interface wasn’t stable above 6.25MHz communication speed.
I was trying to implement Verilog code to using UDP protocol. Firstly according to datasheet and finally I took an Arduino UNO with Ethernet Shield and I did reverse enginnering with Saleae Logic Analyzer. It was using a SPI protocol.
Next I have wrote a state machine in Verilog exactly according to response of Arduino. Now I can sending packets from PC to FPGA but with some difficulties. A C# application is sending UDP packets via W5100 to FPGA. When data is containing bytes e.g. 0X00, 0X55, 0XAA, 0X0F or 0XF0 all is ok and data is the same on the both sides. But when data byte or bytes contains bytes: 0XFD, 0XFE or 0XFF, W5100 return wrong data. I have a LEDs debugger from FPGA to show data and logic analyzer on direct data bus between W5100 and FPGA. Wrong data return W5100 already and FPGA correctly repeating the same wrong data.
Wrong data contain some pseudo-random bits although I read correct address from W5100 memory. When the first message byte contain e.g. 0XFF all other bytes are wrong too and when I’m sending e.g. 0X55 then, all data packet is correct and I can repeate receing process next.
I’m using the same computing algorithm to get receiving address for every byte of receiving message and I get different result for specific byte range.
Wireshark returns the correct message, too. I have no idea why some specific bytes are wrong received from W5100 memory. The 8 byte UDP header is always correct while I’m reading but I didn’t try to set destination IP address or port to this bytes.
I’m sending my state machine in Verilog, too.
Thanks.
W5100.zip (2,7 KB)
