CS deactivate during Parallel mode

We are looking at using the W6100 to replace an older Parallel Ethernet chip in an existing product.
After looking at the data sheet, I would like to know if CS can toggle high between bytes. In the diagrams, it always shows CS low for ADDRH, ADDRL, BS and data bytes which is unusual for processors since they can only keep CS low during device access. The CPU in this case is an older one too. But this is an existing product with a Renesas processor (M3087).


Wiznet chip is supposed to operate only when CS is low.
It can’t change to operate when CS is high.

but can there be a period of CS high between byte accesses?