Spi to ethernet communication.

TCP/IP Chip W5500
21

Why do you think bit 3 will clear itself? I suspect you must write 0x80 to software reset the chip, and not 0x08.

There must not be a delay, there must be a controlled loop instead to wait until CR clears (=command acceptted).

22

Thanks Eugeny for the help,

My mistake…, Actually i did write the value as 0x80 in the code. It was a mistake in my post.

Even reading the version register is giving me wrong value. I don’t know whats happening.

this is the frame i used to read the version register
GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1; // clearing the SCSn to initiate transmission of data

 sdata = 0x00;							//address phase1
 spi_xmit(sdata);
 
 sdata = 0x39;							//address phase2
 spi_xmit(sdata);

 sdata = 0x00;							//Control phase
 spi_xmit(sdata);

     sdata = 0x00;							
 spi_xmit(sdata);

 GpioDataRegs.GPBSET.bit.GPIO57 =1;	// setting high the SCSn to end transmission of data
23

Reading the version register is giving me the values like 0x01FF .
I don’t know whats going wrong in here.

24

could someone please reply?
I have been trying on this for 2 months

25

Sorry for late reply.
When you read the version register of W5500, it must be read the data as 0x04 because the version register is read-only.
The first thing you do is check the right data of version register.

If you don’t read the data as 0x04, SPI isn’t working.

26

Thanks for the help,
What could go wrong in here?
I mean for reading the version register what all initialization is required?
can you tell me that by a pseudo code ?

27

The first thing you do is confirm the connection master and slave as below figure.
image
The second thing you do is send the right W5500 SPI frame whether or not.

You have to set CSn as ‘0’ before SPI data send and if you sent all data, you have to set CSn as ‘1’.

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